1. Field of the Invention
The present invention relates to color-image processing apparatuses and color-image processing methods.
2. Description of the Related Art
There has been known a color-image processing apparatus including a conventional color conversion unit shown in FIG. 1. Three color signals, red (R), green (G), and blue (B) signals, obtained by color-separating an original image are converted to three primary color signals, cyan (C), magenta (M), and yellow (Y) signals, which are used in subtractive mixture of color stimuli, by the color conversion unit shown in FIG. 1. Based on these signals, a color image is printed out by a printing device such as an ink-jet printer.
Signal processing circuits 101, 102, and 103 shown in FIG. 1 generate output C, M, and Y color signals according to three input primary R, G, and B color signals. The signal processing circuits 101, 102, and 103 execute, for example, calculations including a so-called masking operation expressed by the following equations. EQU Circuit 101: C=A.sub.11 .times.R+A.sub.12 .times.G+A.sub.13 .times.B EQU Circuit 102: M=A.sub.21 .times.R+A.sub.22 .times.G+A.sub.23 .times.B EQU Circuit 103: Y=A.sub.31 .times.R+A.sub.32 .times.G+A.sub.33 .times.B
where, A.sub.ij (i, j=1, 2, 3) indicate coefficients determined according to the characteristics of an output device such as a printer.
Unlike this color conversion unit, in which the signal processing circuits 101, 102, and 103 shown in FIG. 1 execute the above-described sum-of-products operation, another color conversion unit has been proposed in which the results of the operation are stored in a table memory in advance and the corresponding results of the operation are read and output according to input R, G, and B signals. In this case, however, when an input signal has eight bits per color, a memory area corresponding to (2.sup.8).sup.3 addresses (namely more than 16 million addresses) is required. This is not practical in terms of memory size.
In contrast, there is also known a color-image processing apparatus including a conventional color conversion unit shown in FIG. 2. Input R, G, and B signals are separated into high-order bit data (R.sub.u, G.sub.u, and B.sub.u) and low-order bit data (R.sub.l, G.sub.l, and B.sub.l) by a high-order and low-order bit separator 110. A table memory 113 stores the results of an operation only for the high-order bit data (R.sub.u, G.sub.u, and B.sub.u). An interpolation circuit 115 applies an interpolation to a C' signal output from the table memory 113 corresponding to the high-order bit data, with the use of the low-order bit data (R.sub.1, G.sub.1, and B.sub.1), and the final output signal C is obtained.
With this configuration, the memory area in the table memory is just required to have the number of addresses corresponding to the number of the high-order bits of the R, G, and B input signals. When each color signal has three high-order bits, for example, a memory area needs to have (2.sup.3).sup.3 addresses (namely, 512 addresses). A memory area required for the table is substantially reduced.
To perform an interpolation, the C' signal output from the table memory 113 actually includes not only a signal corresponding to an address indicated by the high-order bit data (R.sub.u, G.sub.u, and B.sub.u) but also signals corresponding to seven proximal addresses indicated by combinations of the high-order bit R.sub.u, G.sub.u, and B.sub.u signals and, for example, each signal plus 1. The circuit shown in FIG. 2 is used for generating the C signal among the color signals, C, M, and Y. Circuits for generating the M and Y signals are configured in the same way.
Among the above-described conventional apparatuses, the apparatus using the table memory and the interpolation circuit has an advantage in easily implementing complicated non-linear conversion with a relatively small memory capacity. Since the table memory gives actual conversion data only for the specified input signals, however, conversion data for input signals other than the specified input signals is calculated by linear interpolation, thus adding interpolation errors.
To reduce the interpolation errors, it is most effective to increase the number of defining bits plus the high-order bits of input signals used for generating the address of the table memory. When the number of bits is increased by one bit, the number of addresses is also increased accordingly. With R, G, and B inputs, the memory area in the table memory needs to be extended by 2.sup.3 times, namely 8 times.
Therefore, conversion precision and the amount of memory area in the table memory are trade-offs. To reduce the amount of memory, the number of bits needs to be set with conversion precision being reduced to some extent.
As described above, data to be read from the table memory with an input of the high-order bits of input signals is not just one. It is necessary to read the data at the address indicated by the high-order bits and the data at the proximal addresses at the same time.
FIG. 3 is a graph showing the method for reading the table memory and for interpolating the data thereof, using a one-dimensional input for simplicity.
A dotted line 120 indicates a Y signal obtained by converting an input X signal. Values 124 and 125 indicated by triangles on the X-axis representing the input X signal have low-order bits equalling zero and are expressed only by the high-order bits. These points are hereinafter called lattice points. The table memory stores the Y values corresponding to these lattice points. In other words, the table memory stores data corresponding to circles 121 and 123.
When signal X.sub.i is input, the high-order and low-order bit separator separates it into a high-order bit signal and a low-order bit signal. The high-order bit signal generates two lattice points 124 and 125 in the table memory, and output signals Y1 and Y2 are read which are indicated by two hatched circles 123. The interpolation circuit executes an interpolation operation according to the following equation with use of the two-point data and the low-order bit signal X1 of the input signal X.sub.i, and outputs signal Y0. EQU Y0=Y1+(Y2-Y1).times.X1/.DELTA.X (1)
The above description is applied to a one-dimensional input. When an input signal has three-dimensional data including R, G, and B signals, 2.sup.3 =8 proximal data items are required. To read these data items at the same time, a relatively large load is taken in a memory-read circuit.